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Author rhettinger
Recipients lemburg, methane, rhettinger, serhiy.storchaka, terry.reedy, tim.peters, twouters, vstinner
Date 2018-02-15.17:34:48
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Message-id <1518716088.2.0.467229070634.issue32846@psf.upfronthosting.co.za>
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Content 
The 4th graph in this article may be showing the reason for the growth in random access times as the size gets bigger:

https://www.extremetech.com/extreme/188776-how-l1-and-l2-cpu-caches-work-and-why-theyre-an-essential-part-of-modern-chips
History
Date User Action Args
2018-02-15 17:34:48rhettingersetrecipients: + rhettinger, lemburg, tim.peters, twouters, terry.reedy, vstinner, methane, serhiy.storchaka
2018-02-15 17:34:48rhettingersetmessageid: <1518716088.2.0.467229070634.issue32846@psf.upfronthosting.co.za>
2018-02-15 17:34:48rhettingerlinkissue32846 messages
2018-02-15 17:34:48rhettingercreate