Author vstinner
Recipients Yury.Selivanov, casevh, josh.r, lemburg, mark.dickinson, pitrou, rhettinger, serhiy.storchaka, skrah, vstinner, yselivanov, zbyrne
Date 2016-04-22.14:05:45
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Maybe we should adopt a difference approach.

There is something called "inline caching": put the cache between instructions, in the same memory block. Example of paper on CPython:

"Efficient Inline Caching without Dynamic Translation" by Stefan Brunthaler (2009)

Maybe we can build something on top of the issue #26219 "implement per-opcode cache in ceval"?
Date User Action Args
2016-04-22 14:05:46vstinnersetrecipients: + vstinner, lemburg, rhettinger, mark.dickinson, pitrou, casevh, skrah, Yury.Selivanov, serhiy.storchaka, yselivanov, josh.r, zbyrne
2016-04-22 14:05:45vstinnersetmessageid: <>
2016-04-22 14:05:45vstinnerlinkissue21955 messages
2016-04-22 14:05:45vstinnercreate