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Author arigo
Recipients arigo, njs, vstinner
Date 2017-08-04.20:30:33
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Message-id <1501878633.5.0.772183391604.issue31119@psf.upfronthosting.co.za>
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For reference, no, it can't happen on x86 or x86-64.  I've found that this simplified model actually works for reasoning about ordering at the hardware level: think about each core as a cache-less machine that always *reads* from the central RAM, but that has a delay for writes---i.e. writes issued by a core are queued internally, and actually sent to the central RAM at some unspecified later time, but in order.

(Of course that model fails on other machines like ARM.)
History
Date User Action Args
2017-08-04 20:30:33arigosetrecipients: + arigo, vstinner, njs
2017-08-04 20:30:33arigosetmessageid: <1501878633.5.0.772183391604.issue31119@psf.upfronthosting.co.za>
2017-08-04 20:30:33arigolinkissue31119 messages
2017-08-04 20:30:33arigocreate