Message299760
For reference, no, it can't happen on x86 or x86-64. I've found that this simplified model actually works for reasoning about ordering at the hardware level: think about each core as a cache-less machine that always *reads* from the central RAM, but that has a delay for writes---i.e. writes issued by a core are queued internally, and actually sent to the central RAM at some unspecified later time, but in order.
(Of course that model fails on other machines like ARM.) |
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Date |
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2017-08-04 20:30:33 | arigo | set | recipients:
+ arigo, vstinner, njs |
2017-08-04 20:30:33 | arigo | set | messageid: <1501878633.5.0.772183391604.issue31119@psf.upfronthosting.co.za> |
2017-08-04 20:30:33 | arigo | link | issue31119 messages |
2017-08-04 20:30:33 | arigo | create | |
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